Skewing circuit for memory

ABSTRACT

A circuit is provided for transferring a multibyte word of data from a buffer memory to a main memory beginning at any available byte position in the main memory. A gating circuit is controlled in response to an address designating the starting byte position for skewing bytes from the buffer to the starting byte position and to any remaining byte positions of the first addressed word location of the memory. A set of registers and a gating circuit are provided for storing any remaining data bytes from the word read from the buffer. On subsequent transfers, data is transferred simultaneously from the buffer and the register to form a complete word for storage in the main memory and remaining bytes from the buffer are then entered into the register for a subsequent transfer.

United States Patent [$4] SKEWING CIRCUIT FOR MEMORY 4 Claims, 1 DrawingFig.

[52] [1.5. CI 340/1715 [51] Int. Cl 606i l3/00 [50] Field 0! Search...340M725; 235/157 [56] References Cited UNITED STATES PATENTS 3.319.2285/1967 Apple 340/l72.5

BUFFER MEMORY ADDRESS DECODE OR OR MAIN MEMORY 3,346,850 10/1967 Wehrig3,380.030 4/l968 McMahon ABSTRACT: A circuit is provided fortransferring a multibyte word of data from a buffer memory to a mainmemory beginning at any available byte position in the main memory. Agating circuit is controlled in response to an address designating thestarting byte position for skewing bytes from the buffer to the startingbyte position and to any remaining byte positions of the first addressedword location of the memory. A set of registers and a gating circuit areprovided for storing any remaining data bytes from the word read fromthe buffer On subsequent transfers. data is transferred simultaneouslyfrom the buffer and the register to form a complete word for storage inthe main memory and remaining bytes from the buffer are then enteredinto the register for a subsequent transfer.

TIMING I PATENTEUBEB 719m 3.626376 0 2% 1 2 u. 2 m T-0 2 Lu 0 O m 7 IINVENTORS O m LAWRENCE B.ANDERSON 8 ROBERT s. CAPOWSKI m GREGG 0 mm LJOSEPH H. MILLER BY xy/mug ATTORNEY ADDRESS SKEWING CIRCUIT FOR MEMORYINTRODUCTION A memory data transfer called chaining illustrates some ofthe objects of the circuit of this invention and the problems inachieving these objects. When a block of data is to be transferred froman I/O device to a main memory, a block of addresses are assigned to theI/O channel that handles the transfer. If no single block of availableaddresses is large enough to receive the entire transfer, a successionor chain of block addresses is supplied to the channel. In somesituations, the next address is unknown when the channel begins to storedata from the I/O device in the buffer memory of the channel. Thisaddress tells not only the starting word address in the main memory, butit also identifies the starting byte position within the word. Forexample, if it is known that the transfer is to begin at byte position 2of the addressed word location, the buffer loading can begin at its byteposition 2. The first opera tion transfers a partial word from thebuffer to the memory and subsequent operations transfer a word from thebuffer to a word location in the memory. Such an operation isparticularly difiicult with an I/O device such as a magnetic tape unitwhich can not be readily stopped for the interval in which the nextaddress is formed. One object of this invention is to provide means bywhich a buffer can be loaded at its starting ad dress and its contentscan later be transferred to any starting byte position of the mainmemory.

THE INVENTION This invention provides a skewing circuit for transferringthe first bytes of data from a buffer memory to the starting byteposition and any remaining byte locations in the first word location ofthe main memory. Any remaining bytes of the first word of the buffer aretransferred into a register in a position for subsequent transfer todesignated byte locations of the main memory. A decoder for low-orderbit positions of the register holding the starting address controls theskewing circuit. Other bytes of the first word of the buffer are storedin a register. On subsequent transfers, the circuit is controlled totransfer to the memory bytes from the next word of the buffer and thebytes in the register from the preceding word of the buffer. Theregister is then reset and remaining bytes from the buffer are stored inthe register. The circuit is easily adaptable to reading words from thebuffer in their reverse order.

THE DRAWING The single FIGURE in the drawing shows the circuit of thisinvention and associated components of a data processing system.

DETAILED DESCRIPTION Conventional Features The drawing shows a mainmemory I4 and a buffer memory 12 which are interconnected by the circuitof this invention. The buffer memory is part of a data channel andreceives data from an I/O device (not shown) to be transferred to mainmemory I4. An address register which forms part of the channel providesthe main memory address to which the data is to be transferred. Meansnot shown are provided for incrementing or decrementing the address inregister I5 for a block transfer. The channel includes suitable timingmeans (not shown) from which timing signals are derived for use in theskewing circuit of this invention.

In the drawing, memory I4 includes a representation of a word locationof four bytes where the block storage operation is to begin. The nextword location in the block transfer is similarly represented in buffer12. Byte locations in buffer I2 and in memory I4 are designated 0, I, 2and 3. In an example that will be used to simplify the explanation ofthe drawing, the two low-order bits of address register [5 are l O andthe transfer is to begin in byte position 2 of memory 14. Byte positions0 and l of the illustrated word in memory 14 are labeled X to signifythat these positions are not involved in the block transfer and that thebytes stored in these positions are to be preserved. The four bytes ofthe first word of the transfer are designated A, 8, C and D. Bytes A andB are entered into byte positions 2 and 3, and bytes C and D are heldoutside the memory and are to be entered into byte positions 0 and l ofthe next addressed word location. The four bytes of the second word ofthe transfer are designated E, F, G and H and are shown in a wordlocation of buffer I2.

The single output line for each byte position of buffer I2 and inputline for each byte position of memory I4 are representative of aconventional set of wires for the number of bit positions of a byte.Typically, a memory holds eight data bits and one check bit for eachbyte and a line is provided for each bit position for parallel transfer.The circuit that will be discussed next shows the components fortransferring one bit from each byte position. Similar circuits are ofcourse provided for each bit position.

The Address Decode Circuit The two low-order bit positions of registerI5 designate one of the four byte positions as the starting position forthe transfer. A decode circuit I6 is provided to receive the twolow-order bits of address register I5 and to energize one of four outputlines according to an AND logic function of contents of these bitpositions. For example, the upper most line from decode circuit I6,which is labeled 0 0, is energized when the two low-order bits ofregister 15 are 0 0.

The Skew Register A register 17 is provided to hold any bytes of datathat cannot be transferred directly from buffer 12 to main memory 14.Register 17 has three latches l8, l9 and 20; (i.e., one fewer than thenumber of byte positions in buffer I2). A common line connects the threelatches to receive a RESET signal, Each latch is representative of a setof latches for each bit position of the associated byte of buffer 12.The output of each latch is connected to gating circuits (describedlater) for a particular byte position of memory 14. As will be describednext, a set of gating circuits connects the latches to receive data fromappropriate byte positions of buffer 12 according to the output ofdecode circuit I6.

Latch 18 receives data from byte positions I, 2. or 3 of buffer 12 andsupplies an input to byte position 0 of memory I4. It has its l outputconnected to supply a l or 0 to gating circuits (described later) forthe 0 byte position of memory 14. For the example that the drawingillustrates in which the output of decode circuit I6 is l 0, latch [8has its set input connected through an OR-circuit 21 and an AND-circuit22 to byte position 2 of buffer 12. In this example, latch I8 holds abit of byte C, as the legend at the l output of latch I8 shows.Similarly, OR-circuit 21 and an AND-circuit 23 connect the set input oflatch I8 to byte position I of buffer 12 when the decode output is l l,and ORcircuit 2I and an AND-circuit 24 connect the set input of latch 18to byte position 3 of buffer 12 when the decode output is 0 I.

For the example of the drawing in which the decode output is l 0, anOR-circuit 27 and an AND-circuit 28 connect the set input oflatch I9 tobyte position 3 of bufi'er I2 and a bit of byte D appears at the loutput of latch 19. Similarly, AND-circuit 29 connects OR-circuit 27 tobyte position 2 of buffer 12 when the address is l l. Latch 20 receivesan input only when the address is l l, and an AND-circuit 30 connectsthe set input of latch 20 to byte position 3 of buffer I2. A timing linedesignated TIMING II is connected to each AND-circuit 22, 23, 24, 28, 29and 30 to control entry of data into register 17. Main Memory GatingCircuit Byte position 3 of main memory [4 receives inputs directly frombuffer memory I2 for any output of the decode circuit I6. For theexample of the drawing in which the decode output is l 0, OR-circuit 33and an AND-circuit 34 connect memory byte position 3 to bufier byteposition I. When the decode output is l 1, an AND-circuit 35 connectsOR-circuit 33 to buffer byte position 0. When the decode output is 0 I,an ANDcircuit 36 connects OR-circuit 33 to buher byte position 2, andwhen the decode output is 0, and AND-circuit 37 connects OR lcircuit 33to buffer byte position 3.

Memory byte position 2 receives an input either from buffer 12 orregister l7. For the example in which the decode circuit output is I 0.an OR-circuit 40 and an AND-circuit 4] connect memory byte position 2 tobuffer position 0. An AND-circuit 42 connects byte position I of thebuffer to OR-circuit 40 when the decode output is 0 l, and an ANDcircuit43 connects byte position 2 of buffer 12 to OR-circuit 40 when thedecode output is 0 0. An AND-circuit 44 connects the 1 output of latch20 to OR-circuit 40 when the decode output is l 1.

Memory byte position 1 receives an input from either byte position 0 orI of buffer memory 12 or from latch 19. For the example of the drawing,an OR-circuit 47 and an AND-circuit 48 connect memory byte position I tothe output of latch 19. An AND-circuit 49 connects OR-circuit 47 to theoutput of latch I9 when the decode circuit output is l I. When thedecode output is 0 l, and AND-circuit 50 connects OR-circuit 47 to byteposition 0 of buffer 12; and when the decode output is 0 0, andAND-circuit 51 connects OR-circuit 47 to byte position I of buffer 12.

Memory byte position 0 receives an input either from byte position 0 ofbuffer 12 or from latch 18 of register 17. In the example in which thedecode output is l 0. an Oil-circuit 53 and an AND-circuit 54 connectbyte position 0 to latch 18. An AND-circuit 55 connects OR-circuit 53 tobyte position 0 of buffer II when the decode output is 0 0. AND-circuits56 and 57 provide a data path from latch 18 to OR-circuit 53 when thedecode output is either 0 l or I l.

Each AND-circuit is also controlled by a line designated TIMING I forcontrolling the entry of data into memory 14 from bufier l2 and register17.

Operation In the operation of the apparatus of the drawing, the buffermemory I2, main memory I4, and address register I are operated in a waythat is conventional for a direct transfer between buffer 12 and memoryl4. In the first step of the transfer of the two words illustrated inthe drawing, the bufl'er memory 12 is controlled to undergo a readoperation that produces bytes A, B, C and D on the lines from buffer 12.The TIMING I line is energized to transfer data from bufier 12 directlyto main memory 14 and to transfer data from latches I7 and 18 to memory14. Thus, AND-circuits 41 and 34 are conditioned to transfer data A andB from byte positions 0 and l of buffer 12 to byte positions 2 and 3 ofmemory I4. AND- circuits 48 and 54 are also conditions to transfer datafrom latches l8 and 19 in skew register I7 to byte positions 0 and 1 ofmemory 14. Since the bytes designated X in positions 0 and l of thisword of memory I4 are to be preserved, the memory 14 is controlled (asis conventional) to produce a write operation only in byte positions 2and 3 and to not write into byte positions 0 and l. The TIMING I line isthen deenergized and the RESET line of register 17 is energized to resetlatches 18, I9 and 20. The TIMING II line is then energized to conditionAND-circuits 22 and 28 to transfer bytes C and D from buffer bytepositions 2 and 3 to latches l8 and 19. The TIMING II line is thendeenergized and buffer I2 is operated to produce the next read operationwhich produces bytes E, F G and H at its output. Thus, the operation asit has been described so far produces the data state that legend in thedrawing illustrate.

Each additional transfer is identical to the transfer described exceptthat memory 12 is controlled to produce a store operation in each byteposition. During the first part of the next operation, the TIMING I lineis energized to transfer bytes E and F directly from byte positions 0and l of buffer memory to byte positions 2 and 3 of the main memory andsimultaneously to transfer bytes C and D from latches l8 and I9 tomemory byte positions 0 and l. The TIMING l line is deenergized,register 17 is reset. and the TIMING Il line is energized to conditiongates 24 and 28 to transfer bytes G and H from positions 2 and 3 in thebuffer memory to latches l8 and 19.

For read backwards. decode circuit l6 produces outputs that are 1 higherthan the input. (Input I 1 produces output 0 0). For example. for decodeinput 0 l and output I 0, bytes E, F, G and H are read first and stored,as already described, with the last byte. H, in the starting position, 0l.

Additional registers may be provided for transfers between a buffer andmemory of different word size. For example, if the memory stores a wordof eight bytes, the two word operation just described would store bytesA, B, C, D, E and F in the eight-byte register and would store bytes Gand H in register 17. The operation could similarly be started in thesecond half of the eight-byte register.

From the preferred embodiment of the invention and specific variationssuggested, those skilled in the art will recognize various applicationsand modifications of the circuit within the spirit of the invention andthe scope of the claims.

What is claimed is:

I. A circuit for transferring a sequence of multibyte words from a firstmemory to a second memory having multibyte word locations bypredetermined bits of an address in said second memory defined anaddress register, comprising:

a signal line for each byte position in said second memory,

and address decoder means responsive to said predetermined bits in saidaddress register for producing a signal on the one of said linesidentifying said starting byte position;

a multibyte register having one fewer byte positions than a word of saidfirst memory,

means responsive to said signal for transferring bytes from a word readfrom said first memory to said starting byte position in said secondmemory and any available subsequent byte positions in a word location;

means responsive to said signal for transferring to said register anyremaining bytes of a word of said first memory; and

means responsive to said signal for transferring any bytes in saidregister to the following byte positions in said second memory.

2. The circuit of claim I including timing means for initiating thetransfer of any bytes from said register and bytes from said firstmemory to said multibyte location and thereafter transferring said anyremaining bytes to said register.

3. The circuit of claim 2 in which said means for transferring bytes tosaid register comprises gating means responsive to a said signal on saidsignal lines and to said timing means for transferring selected bytepositions of said buffer to said register.

4. The circuit of claim 3 in which said second memory and said firstmemory have equal numbers of bytes in a stored word.

i I I. i G

1. A circuit for transferring a sequence of multibyte words from a firstmemory to a second memory having multibyte word locations starting at abyte position said second memory defined by predetermined bits of anaddress in an address register, comprising: a signal line for each byteposition in said second memory, and address decoder means responsive tosaid predetermined bits in said address register for producing a signalon the one of said lines identifying said starting byte position; amultibytE register having one fewer byte positions than a word of saidfirst memory; means responsive to said signal for transferring bytesfrom a word read from said first memory to said starting byte positionin said second memory and any available subsequent byte positions in aword location; means responsive to said signal for transferring to saidregister any remaining bytes of a word of said first memory; and meansresponsive to said signal for transferring any bytes in said register tothe following byte positions in said second memory.
 2. The circuit ofclaim 1 including timing means for initiating the transfer of any bytesfrom said register and bytes from said first memory to said multibytelocation and thereafter transferring said any remaining bytes to saidregister.
 3. The circuit of claim 2 in which said means for transferringbytes to said register comprises gating means responsive to a saidsignal on said signal lines and to said timing means for transferringselected byte positions of said buffer to said register.
 4. The circuitof claim 3 in which said second memory and said first memory have equalnumbers of bytes in a stored word.